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verilator: fix typo (#9559)

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K.B.Dharun Krishna 2022-11-29 00:06:58 +05:30 committed by GitHub
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@ -1,6 +1,6 @@
# verilator # verilator
> Converts Verilog and SystemVerilog hardware description language (HDL) designs into a C++ or SystemC model that after compiling can be executed. > Converts Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling.
> More information: <https://veripool.org/guide/latest/>. > More information: <https://veripool.org/guide/latest/>.
- Build a specific C project in the current directory: - Build a specific C project in the current directory: