mirror of https://github.com/CrimsonTome/tldr.git
21 lines
743 B
Markdown
21 lines
743 B
Markdown
# verilator
|
|
|
|
> Converts Verilog and SystemVerilog hardware description language (HDL) design into a C++ or SystemC model to be executed after compiling.
|
|
> More information: <https://veripool.org/guide/latest/>.
|
|
|
|
- Build a specific C project in the current directory:
|
|
|
|
`verilator --binary --build-jobs 0 -Wall {{path/to/source.v}}`
|
|
|
|
- Create a C++ executable in a specific folder:
|
|
|
|
`verilator --cc --exe --build --build-jobs 0 -Wall {{path/to/source.cpp}} {{path/to/output.v}}`
|
|
|
|
- Perform linting over a code in the current directory:
|
|
|
|
`verilator --lint-only -Wall`
|
|
|
|
- Create XML output about the design (files, modules, instance hierarchy, logic and data types) to feed into other tools:
|
|
|
|
`verilator --xml-output -Wall {{path/to/output.xml}}`
|